1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to the shape and arrangement of storage node electrodes of the charge-storage capacitors in a DRAM comprising memory cells each consisting of a transistor and a stacked-type charge-storage capacitor.
2. Description of the Prior Art
DRAM stores information as an electric charge in charge-storage capacitors. From the viewpoint of stable operation and the memory retention time, it is desired to make the capacitance of the charge-storage capacitor as large as possible. On the other hand, it is needed for higher integration of DRAM to miniaturize the memory cell, accompanied by to smaller allowable projective plane area for the charge-storage capacitor. The projective plane area is smaller than the size of the memory cell. For solving this contradiction, in the DRAM comprising memory cells each consisting a transistor and a charge-storage capacitor, as the structure of the charge-storage capacitor became used firstly planar type, followed by trench type, and then stacked type. With deeper trench, the trench-type charge-storage capacitor can have larger side-face area accompanied by increasing capacitance. The stacked-type charge-storage capacitor can have larger capacitance due to the storage node electrode essentially higher or thicker, and hence having larger side face area. The newest stacked-type charge-storage capacitor is intended to have further increased capacitance by the use of fin-structured storage node electrode. (Fin-structure has been impossible to be applied to trench type.) Unless specified structure such as fin-structure is taken into consideration, the capacitance of the charge-storage capacitor depends only on the surfaces of the top and side faces of the storage node electrode.
Of recent stacked-type DRAMs, the most compact one is exemplified in IDEM Technical Digest pp. 596-599, 1988.
On the surface of a p-type substrate, word lines parallel to the X-axis and bit lines parallel to the Y-axis orthogonal with the X-axis are formed as a matrix arrangement. The size of the memory cell in the DRAM is 2Pw.times.P.sub.B, Pw being the pitch of the word lines (the word line width plus the distance between the word lines) and P.sub.B being the pitch of the bit lines (the bit line width plus the distance between the bit lines). An active area is formed of, for example, an area defined by the ith and i+1th bit lines and the jth and j+1th word lines, for example, an area defined by the i+1th and i+2th bit lines and the j+2th and j+3th word lines, and an area connecting between these areas. This active area includes a n.sup.+ -type self-aligned diffusion regions. The n.sup.+ -type diffusion region defined by the ith and i+1th bit lines and the jth and j+1th word lines serves as node diffusion region for (i+1, J+1) bit. The n.sup.+ -type diffusion region between j+1th and j+2 word lines serves as bit diffusion region for (i+1, J+1) bit and (i+1, j+2) bit. The n.sup.+ -type diffusion region defined by i+1th and i+2the bit lines and j+2th and j+3th word lines serves as node diffusion region for (i+1, j+2) bit. The j+1th word line, the node diffusion region for (i+1, J+1) bit, and the bit diffusion region for (i+1, J+1) bit and (i+1, J+1) bit constitute a transistor for (i+1, j+1) bit. Similarly the j+2th word line, the node diffusion region for (i+1, J+2) bit, and the bit diffusion region for (i+1, J+1) bit and (i+1, J+2) bit constitute a transistor for (i+1, j+2) bit.
The bit diffusion region for (i+1, J+1) bit and (i+1, J+2) bit is provided with a bit contact hole connecting to i+1th bit line. The node diffusion region for (i+1, j+1) bit is provided with a storage node contact hole connecting to the storage node electrode for a charge-storage capacitor of (i+1, j+1) bit. The node diffusion region for (i+1, j+2) bit is provided with a storage node contact hole connecting to the storage node electrode for a charge-storage capacitor of (i+1, j+2) bit. The top faces of the storage node electrodes of these charge storage capacitors project generally rectangles on the surface of the silicon substrate. Of the rectangle, the major sides are parallel to bit lines or Y-axis and the minor sides to word lines or X-axis.
In such a stacked-type DRAM, the capacitance of a charge-storage capacitor is created by a storage node electrode, a cell plate electrode and a capacitive dielectric film between these electrodes. The capacitance value of the charge-storage capacitor depends on the dielectric constant and the thickness of the capacitive insulating film, and the electrode area which is the area of the opposed surfaces of the storage node electrode and the cell plate electrode. Assuming capacitive insulating film is of a certain kind and has a fixed thickness, then only increase of the electrode area is responsible for increase in the capacitance value of this capacitor. The electrode area is equal to the surface area of the storage node electrode.
Of the storage node electrode, the surface area A.sub.T0 is the sum of the area A.sub.t0 of the top face and the area A.sub.s0 of the side face. Strictly speaking, the top face is a curved surface which projects an area smaller than the cell size 2Pw.times.P.sub.B on the surface of the silicon substrate. Using minimum feature size for fabricating this DRAM, F, as the distance between two storage node electrodes gives the maximum value of A.sub.T0. Under this condition, the top face projects a rectangle of which the major sides are parallel to bit lines on the silicon substrate surface. The rectangle has an area of (2Pw-F).times.(P.sub.B -F) and a perimeter, L.sub.P0, of 2.times.(2Pw+P.sub.B -2F). Assuming d in the film thickness or height of the storage node electrode, the area of the size face, A.sub.s0, is given as 2.times.(2Pw+P.sub.B -2F).times.d.
The conventional method for increasing the surface area of the storage node electrode, A.sub.T0, is generally to reduce F, especially to increase d. Further increase of it can be achieved by forming irregularities on the top and side faces. Such methods for increasing the storage node electrode surface area, A.sub.T0, however, involve process of fabrication, and thus the increase of A.sub.T0 is limited by the manufacture techniques of the times so far as the shape and arrangement of storage node electrodes in the prior art are used. In other wores, it is impossible to increase the perimeter and also the surface area A.sub.T0 of the storage node electrode independent of manufacture techniques.